1. Field of the Invention
The present invention relates to a semiconductor device having a trench gate VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor) and a method of manufacturing the same.
2. Description of Related Art
A VDMOSFET (trench gate VDMOSFET) employing a trench gate structure is generally known as a MOSFET having a high withstand voltage.
FIG. 10 is a schematic sectional view of a conventional semiconductor device 101 having a trench gate VDMOSFET.
The semiconductor device 101 includes an N+-type substrate 102. An N−-type epitaxial layer 103 is stacked on the N+-type substrate 102. A P−-type body region 104 is formed in a surface layer portion of the epitaxial layer 103.
A trench 105 is dug in the epitaxial layer 103 from the surface thereof. The trench 105 penetrates the body region 104, so that the deepest portion thereof reaches the epitaxial layer 103 under the body region 104. A gate electrode 107 made of polysilicon doped with an N-type impurity in a high concentration is embedded in the trench 105 through a gate insulating film 106.
N+-type source regions 108 are formed in a surface layer portion of the body region 104 along the trench 105. A P+-type contact region 109 is formed on each N+-type source region 108 to penetrate the N+-type source region 108.
A drain electrode 110 is formed on the back surface of the N+-type substrate 102.
When the source region 108 and the body contact region 109 are grounded and the potential of the gate electrode 107 is controlled while a positive voltage of a proper level is applied to the drain electrode 110, a channel is formed in the vicinity of the interface between the body region 104 and the gate insulating film 106, and a current flows between the source region 108 and the drain electrode 110.
In the steps of manufacturing the semiconductor device 101, a silicon oxide film is formed on the surface of the epitaxial layer 103 including the inner surface of the trench 105. Then, the gate electrode 107 made of doped polysilicon is formed on the silicon oxide film in the trench 105. Thereafter HF (hydrofluoric acid) is supplied to the surface of the portion of the silicon oxide film located outside the trench 105 to remove this portion of the silicon oxide film in advance of ion implantation for forming the N+-type source region 108. At this time, the upper end portion of the silicon oxide film located in the trench 105, i.e., the upper end portion of the gate insulating film 106 is also removed by HF, to result in a portion where the gate electrode 107 and the N+-type source region 108 are opposed to each other without through the gate insulating film 106. In the conventional semiconductor device, therefore, the withstand voltage (gate-to-source withstand voltage) between the gate electrode 107 and the N+-type source region 108 is disadvantageously reduced.
The body region 104 is formed by implanting (ions of) a P-type impurity into the epitaxial layer 103 from the surface thereof and thereafter drive-in-diffusing the P-type impurity. Thus, the body region 104 has such an impurity concentration profile that the P-type impurity concentration is extremely low in the vicinity of the interface between the body region 104 and the epitaxial layer 103 under the body region 104 and higher on the surface layer side. Therefore, a depletion layer largely spreads toward the source region 108, to easily cause the so-called punch through.
If the trench gate VDMOSFET is provided on the N+-type substrate 102 mixedly with a planar gate MOSFET, however, the portion for forming the body region 104 must be selectively of the P type, and hence the body region 104 must inevitably be formed by implanting the P-type impurity into the epitaxial layer 103 and diffusing the same.